Intern Digital Engineer
Renesas Electronics
- Львів
- Стажування
- Повна зайнятість
- Participate in feasibility studies and sub-block/chip-level architecture definition
- Design and integration of digital sub-blocks at top-level
- Support DFT strategy and implementation
- Work closely with back-end designers to correctly implement digital designs to layout
- Verification planning, verification methodology and test bench development using Verilog/VHDL
- Static timing analysis (STA), formal verification, logic equivalence checking
- Lab evaluation and debug of digital blocks and full chip function
- Tape out database and document preparation
- Bachelor's or master's degree student in Electrical Engineering or related disciplines
- Preferably some experience in design of analog/digital circuits (0−1 for junior designers)
- Knowledge of Xcelium,(System)Verilog/VHDL/scripting languages
- Full understanding of IC design flow
- Ability to prioritize work, set goals and meet deadlines
- Self-motivated and take full responsibility for solutions
- Good written, communication and teamwork skills
- (pre-)intermediate English level
- Familiarity with Cadence Virtuoso
- Experience with IC technologies, DFT or protocols (UART, I2C, SPI, etc.)
- Knowledge of transistor-level integrated circuits and semiconductor physics
- Understanding of advanced verification methodologies (e.g. UVM, ABV)
- Familiarity with RTL logic design, design constraints, synthesis, P&R, static timing analysis and formal verification
- Friendly and highly professional team;
- 14 calendar days paid vacation;
- Flexible working hours;
- Professional & personal growth.